Apple's Cyclone Microarchitecture Detailedby Anand Lal Shimpi on March 31, 2014 2:10 AM EST
The most challenging part of last year's iPhone 5s review was piecing together details about Apple's A7 without any internal Apple assistance. I had less than a week to turn the review around and limited access to tools (much less time to develop them on my own) to figure out what Apple had done to double CPU performance without scaling frequency. The end result was an (incorrect) assumption that Apple had simply evolved its first ARMv7 architecture (codename: Swift). Based on the limited information I had at the time I assumed Apple simply addressed some low hanging fruit (e.g. memory access latency) in building Cyclone, its first 64-bit ARMv8 core. By the time the iPad Air review rolled around, I had more knowledge of what was underneath the hood:
As far as I can tell, peak issue width of Cyclone is 6 instructions. That’s at least 2x the width of Swift and Krait, and at best more than 3x the width depending on instruction mix. Limitations on co-issuing FP and integer math have also been lifted as you can run up to four integer adds and two FP adds in parallel. You can also perform up to two loads or stores per clock.
With Swift, I had the luxury of Apple committing LLVM changes that not only gave me the code name but also confirmed the size of the machine (3-wide OoO core, 2 ALUs, 1 load/store unit). With Cyclone however, Apple held off on any public commits. Figuring out the codename and its architecture required a lot of digging.
Last week, the same reader who pointed me at the Swift details let me know that Apple revealed Cyclone microarchitectural details in LLVM commits made a few days ago (thanks again R!). Although I empirically verified many of Cyclone's features in advance of the iPad Air review last year, today we have some more concrete information on what Apple's first 64-bit ARMv8 architecture looks like.
Note that everything below is based on Apple's LLVM commits (and confirmed by my own testing where possible).
|Apple Custom CPU Core Comparison|
|Apple A6||Apple A7|
|ARM ISA||ARMv7-A (32-bit)||ARMv8-A (32/64-bit)|
|Issue Width||3 micro-ops||6 micro-ops|
|Reorder Buffer Size||45 micro-ops||192 micro-ops|
|Branch Mispredict Penalty||14 cycles||16 cycles (14 - 19)|
|Load Latency||3 cycles||4 cycles|
|Indirect Branch Units||0||1|
|L1 Cache||32KB I$ + 32KB D$||64KB I$ + 64KB D$|
As I mentioned in the iPad Air review, Cyclone is a wide machine. It can decode, issue, execute and retire up to 6 instructions/micro-ops per clock. I verified this during my iPad Air review by executing four integer adds and two FP adds in parallel. The same test on Swift actually yields fewer than 3 concurrent operations, likely because of an inability to issue to all integer and FP pipes in parallel. Similar limits exist with Krait.
I also noted an increase in overall machine size in my initial tinkering with Cyclone. Apple's LLVM commits indicate a massive 192 entry reorder buffer (coincidentally the same size as Haswell's ROB). Mispredict penalty goes up slightly compared to Swift, but Apple does present a range of values (14 - 19 cycles). This also happens to be the same range as Sandy Bridge and later Intel Core architectures (including Haswell). Given how much larger Cyclone is, a doubling of L1 cache sizes makes a lot of sense.
On the execution side Cyclone doubles the number of integer ALUs, load/store units and branch units. Cyclone also adds a unit for indirect branches and at least one more FP pipe. Cyclone can sustain three FP operations in parallel (including 3 FP/NEON adds). The third FP/NEON pipe is used for div and sqrt operations, the machine can only execute two FP/NEON muls in parallel.
I also found references to buffer sizes for each unit, which I'm assuming are the number of micro-ops that feed each unit. I don't believe Cyclone has a unified scheduler ahead of all of its execution units and instead has statically partitioned buffers in front of each port. I've put all of this information into the crude diagram below:
Unfortunately I don't have enough data on Swift to really produce a decent comparison image. With six decoders and nine ports to execution units, Cyclone is big. As I mentioned before, it's bigger than anything else that goes in a phone. Apple didn't build a Krait/Silvermont competitor, it built something much closer to Intel's big cores. At the launch of the iPhone 5s, Apple referred to the A7 as being "desktop class" - it turns out that wasn't an exaggeration.
Cyclone is a bold move by Apple, but not one that is without its challenges. I still find that there are almost no applications on iOS that really take advantage of the CPU power underneath the hood. More than anything Apple needs first party software that really demonstrates what's possible. The challenge is that at full tilt a pair of Cyclone cores can consume quite a bit of power. So for now, Cyclone's performance is really used to exploit race to sleep and get the device into a low power state as quickly as possible. The other problem I see is that although Cyclone is incredibly forward looking, it launched in devices with only 1GB of RAM. It's very likely that you'll run into memory limits before you hit CPU performance limits if you plan on keeping your device for a long time.
It wasn't until I wrote this piece that Apple's codenames started to make sense. Swift was quick, but Cyclone really does stir everything up. The earlier than expected introduction of a consumer 64-bit ARMv8 SoC caught pretty much everyone off guard (e.g. Qualcomm's shift to vanilla ARM cores for more of its product stack).
The real question is where does Apple go from here? By now we know to expect an "A8" branded Apple SoC in the iPhone 6 and iPad Air successors later this year. There's little benefit in going substantially wider than Cyclone, but there's still a ton of room to improve performance. One obvious example would be through frequency scaling. Cyclone is clocked very conservatively (1.3GHz in the 5s/iPad mini with Retina Display and 1.4GHz in the iPad Air), assuming Apple moves to a 20nm process later this year it should be possible to get some performance by increasing clock speed scaling without a power penalty. I suspect Apple has more tricks up its sleeve than that however. Swift and Cyclone were two tocks in a row by Intel's definition, a third in 3 years would be unusual but not impossible (Intel sort of committed to doing the same with Saltwell/Silvermont/Airmont in 2012 - 2014).
Looking at Cyclone makes one thing very clear: the rest of the players in the ultra mobile CPU space didn't aim high enough. I wonder what happens next round.
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errorr - Monday, March 31, 2014 - linkSeems more like wishful thinking or paranoia. Apple is a consumer electronics company that sells premium computers in several form factors. They are a luxury brand. They have no real interest in segmentation at the low margin price competitive end. Why would you assume that they have completely changed the culture of the company so much? Would BMW or Land Rover hurt their brand by building cheap cars that make low margins?
name99 - Monday, March 31, 2014 - linkIs there good reason to believe that Maxwell offers a better performance/power tradeoff than Imagination? Maxwell may well be a kickass architecture for 300W, but scaling it down to 3W doesn't mean it's now competitive with something designed to peak at 3W and to usually operate a whole lot lower.
Apple has always been a lot more interested in decent efficiency than in simply being able to boast that it can handle more pixels (or triangles, or MACs or whatever) than anyone else.
Death666Angel - Monday, March 31, 2014 - linkAre you reading Anandtech article? The Maxwell article clearly states that it is design "mobile first", so the TDP target when designing wasn't 300W, but an order of magnitude below that at least.
Anders CT - Tuesday, April 1, 2014 - link@name99
If Apple is so concerned about efficiency, why are they making large,complex, dual-core, out-of-order, "desktop-class" CPUs for their smartphones?
Because they prioritise single-threaded performance higher, which happens to have the largest impact on user interface responsiveness. The most power-efficient design is the octo-core cortex-a7. It has exceptional computational power pr watt.
PeteH - Tuesday, April 1, 2014 - link@Anders CT
How many mobile programs (or even desktop ones for that matter) to a good job of multithreading? Exceptional computational power per watt because of 8 cores doesn't mean a lot if everything you're running is single threaded.
mczak - Monday, March 31, 2014 - linkJust a small correction, intel doesn't use Rogue for BT (Bay Trail) platform. Only the smartphone SoCs (Merrifield, successor Moorefield) do, the tablet SoCs (Bay Trail-T, successor Cherry Trail-T) feature intel's own graphics (gen7 for Bay Trail, gen8 for Cherry Trail).
microcolonel - Monday, March 31, 2014 - linkI'm pretty sure BayTrail doesn't use a PowerVR GPU at all, they're using their in-house Intel HD Graphics system(the one that they put into their Core CPUs). It was their /old/ atoms which used PowerVR.
toyotabedzrock - Tuesday, April 1, 2014 - linkMaybe that is why they removed that code name from the roadmap. NV would jump at a chance like that, provided they could handle not getting massive branding rights from apple.
rstat1 - Sunday, April 6, 2014 - linkBay Trail is actually the first Atom that DOESN'T use crappy PowerVR graphics. Instead it uses a cut down version of IVB's GPU.
techconc - Monday, March 31, 2014 - linkAnything is possible, but it seems unlikely that Apple would switch to ARM for their Mac lineup. Having a device that can boot into Windows natively has been a marketing advantage and helpful for "switchers" that still rely on a given piece of Windows software.
More likely, I'd expect the iOS product line to become more "professional" (whatever that means) to the point where the capabilities between desktop and mobile product lines are blurred. I see iOS as being more of a forward looking approach to doing things, etc.