AMD’s Special Sauce: A1100’s Co-Processors

This year, AMD has answered some critics of their business by describing their plans to regain a differentiated position on the market. One of the key slides AMD used to described its position showed ARM, GPU, and x86 cores at the center surrounded by complementary IP.

AMD’s argument is it is uniquely positioned as the only chip company with powerful graphics, ARM and x86 CPU designs, a server heritage including security and fabric (thanks SeaMicro), as well as extensive chip packaging, motherboard and server design expertise. 

The complementary IP AMD brings to the A1100 is two Co-Processors. The Cryptographic CoProcessor (CCP) and the System Control Processor (SCP). 

While the Cortex A57s include cryptographic instructions courtesy of the ARMv8 ISA, there are times when a server has significant cryptographic load and it is better to offload that to a coprocessor than service it directly on the CPU core. Cryptographic transactions such as https are well suited for the CPU core as they require low latency and the overhead to offload the work often negates the acceleration the coprocessor provides. However, cryptographic transactions such as archive compression/decompression and large data set encryption/decryption can benefit tremendously.

Utilizing the coprocessor requires operating system awareness to redirect cryptography functions to the dedicated hardware instead of doing them with the general purpose hardware. For example, requesting a random number from the OS would ideally fetch it from the CCP. AMD has already committed an update to the Linux 3.14 kernel to support this.

The SCP is based around an ARM Cortex-A5 processor and is effectively an SoC itself inside the A1100 SoC. The rest of the A1100 communicates to the SCP as if it is an IO device. This seems weird, but the isolation is by design. There are two reasons for this: Out-of-band management, and secure processing with ARM TrustZone technology.

Out-of-band management is a technique used in industry for servicing and diagnosing deployed systems regardless of the state of its normal operation or ‘in-band’ components. The SCP has its own dedicated 10/100/100 Ethernet connection, RAM, ROM, and IO connectivity. Connecting from a management interface, a user can read and configure motherboard devices like temperature sensors, power supplies, and fans completely independent from the rest of the A1100 SoC’s activities. Since the SCP is also core to the boot process, server administrators can also reset servers remotely.

One of the other reasons the SCP exists it to implement ARM's TrustZone technology. AMD announced two years ago they would be partnering with ARM to implement TrustZone technology into future CPUs, and this is the first server CPU to receive the feature. This processor is actually already present in AMD’s x86s APUs. To recap, TrustZone is an ARM technology providing a ‘secure world’ inside the SoC. Programming routines requiring utmost security, like digital rights management, can execute inside the SCP and are protected from unauthorized access from the ‘normal world’. These features are typically found in consumer devices, as certain applications like Netflix require a secure processing path to play HD content. AMD likely reused their TrustZone processor design from consumer APUs to implement the SCP, and it will be interesting to see how server software takes advantage of it.

Introduction and the A1100 Reference Design and Final Words
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  • Gigaplex - Monday, August 11, 2014 - link

    I'm not sure why you'd want Storage Spaces. The marketing sounds great, but there are many complaints all over the web that it just doesn't work as well as advertised. Parity mode in particular has unusably slow write speeds, and you can't expand the pool in an ad hoc fashion as was originally advertised - you have to add a collection of drives simultaneously which effectively just builds a second pool. And don't even ask about rebalancing. Conventional RAID5 is actually more flexible in practice.
  • hechacker1 - Tuesday, August 12, 2014 - link

    The latest Server2012 updates have largely fixed it. Yes, it's slow, but that's for data consistency. If you enable SSD tiering, I can max out my network connection. Or you can enable the ram write cache, if you have a UPS.

    The biggest problem is rebalancing, which it doesn't do. It also can't shrink a volume to safely remove a drive. But a lot of other RAID schemes don't support that either.
  • easp - Tuesday, August 12, 2014 - link

    Keep in mind that Microsoft has quite a few servers of their own for Azure, Bing, etc. Thats the initial target market for this stuff, orgs that run their own software on big infrastructure.
  • En1gma - Monday, August 11, 2014 - link

  • davegraham - Monday, August 11, 2014 - link

    Stephen, you also have to remember that AMD has separate divisions now (retail and embedded). the Embedded side absolutely could and will integrate into SeaMicro. ;) so, just remember, a dev kit isn't anything more than that....a dev kit. the final integration stages remain to be seen.
  • Stephen Barrett - Monday, August 11, 2014 - link

    I agree with you completely. I was just hoping they would make a big announcement on that simultaneously instead of the weak reference system shown.
  • BMNify - Monday, August 11, 2014 - link

    amd seem to have killed mass consumer/prosumer/SME uptake before they even start as these reference system designed 2U kit are being sold for 3000+ USD.

    selling your initial reference boards for to high a price massivly limits AMD's ability to mass produce these soc quickly at a good mass consumer price ($200 per chip for testing and product OEM development etc) so no initial mass uptake, and far longer time scales to get parity with other mass produced customer hardware, remember its an untested soc, and they need to prove its viability PDQ to make their ROI back and pay their bills etc...
  • iwod - Monday, August 11, 2014 - link

    I must have missed it, why is it not targeting webserver application market?

    I find myself asking the same question whenever there is an ARM Server SoC article. What exactly does A1100 does better then Intel's Airmont based Server SoC? Yes, Airmont, the "14nm" version of Silvermont, compared to 28nm of A1100.
  • Wilco1 - Monday, August 11, 2014 - link

    We can only compare it with Avoton for now as details for Airmont are not known yet. And it should be a good deal faster than Avoton (especially given it has 3x the amount of L2/L3 cache) and at better perf/W. Whether Airmont increases performance is unclear, power is likely reduced, but so 20 or 16nm versions of Seatle might be available next year as well, and those would significantly increase clockspeed.
  • tuxRoller - Monday, August 11, 2014 - link

    Wow. If this a video accelerator, this would be a tremendous soc for a media server/nas.
    All those sata ports, 10Gbe ports(!!!), ecc ram, and better performance/clock than silvermont when using the new isa.

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