MIPS Instruction Set: 64-bit Release 6

Computer processors accomplish tasks by following instructions. The processor, however, only understands instructions in a specific "language". The language of a processor is called its Instruction Set Architecture (ISA). The code sent to a processor must be in that ISA to be understood. It's similar to what would happen if someone proceeded to give me instructions in Portuguese: I unfortunately would have no idea how to execute them. When a program or operating system is authored and compiled, the compiler is parameterized to generate the 1s and 0s of binary code using a specific ISA.

In general, there are two types of ISAs. Complex Instruction Set Computing (CISC) and Reduced Instruction Set Computing (RISC).  The difference between them being of course their relative complexity. In general, a RISC ISA contains significantly fewer instructions that are far simpler than a CISC ISA.

Despite its increased complexity, CISC actually predates RISC and was only named retroactively. CISC ISAs were a necessity when low level code (assembly) was often authored by hand, and compilation was crippled by dramatically less powerful compilers than those available today. Having higher level instructions in the ISA, such as looping, allowed simple compilers to extract sufficient performance and human assembly authors to write programs. The most popular CISC ISA ever written is the x86 ISA used in Intel, AMD, and VIA processors. Interestingly, these processors now use dedicated decoding hardware to actually translate CISC instructions into RISC instructions that are executed internally.

RISC ISAs push much of the instruction complexity into the code compiler. Instead of using instruction decode circuits inside the CPU core to translate complex instructions into simple ones, RISC processors operate directly on the simple instructions provided by the compiler. This benefit is somewhat offset as often code compiled for RISC ISAs is larger; it may take multiple RISC instructions for the equivalent CISC instruction. This holds true in computer science theory, as one of the first things taught is there is often a tradeoff between storage and efficiency. If there is a desire for increased efficiency, precompute items ahead of time and then store them. If you need to save storage (or reduce the memory footprint), compute items on-the-fly.

The most popular RISC ISA ever written is the ARM ISA. The MIPS ISA, like ARM, is RISC. It has been revised several times since its inception in 1985. The first five releases are named according to roman numerals I through V, and each was a super set of the last. In 1999, MIPS announced a large revision of the ISA which deprecated the old hierarchical I through V scheme and instead focused on two ISAs: MIPS32 and MIPS64.

Release 6 occurred in 2014 and the I6400 is the first CPU utilizing the new ISA. I won’t go through all the changes in the ISA, but the most significant is a culling of the instructions. Significant work was done to simplify the ISA by removing infrequently used instructions, in particular those that overlapped with Imagination’s PowerVR GPUs. Additional instructions were also added specifically targeting today’s applications like web browsers. The fruit of these instructions has recently been seen as Google Chrome’s V8 rendering engine added experimental support for MIPS64 release 6 in July.

In the MIPS programmer’s guide the release 6 ISA is actually referred to as MIPS3264 release 6. This naming is not by accident, as MIPS64 ISA is actually a direct superset of the MIPS32 ISA. In contrast to AMD64 (x86-64), there are no "operating modes" that dictate the bitness of instructions executed on the CPU but rather an entirely new set of instructions specifically for 64-bit. Registers inside the CPU are all 64bit, and when a 32-bit instruction executes, results saved in registers are sign-extended to the entire 64-bits of space. This means there is no mode switching, and 32-bit and 64-bit applications can coexist and even be executed using the same hardware resources like registers (more on this later).

The MIPS ISA contains several optional instructions called Application Specific Extensions. These rely on optional portions of the CPU core that a licensee may or may not implement. Additionally, a MIPS CPU has optional modules that can enhance performance when paired with certain instructions.

Release 6 drops the legacy MIPS16e ASE as well as the redundant 3D ASE now that Imagination offers GPUs alongside MIPS CPUs.

MIPS CPUs in Mobile Devices

While MIPS CPUs are quite popular in networking equipment and many other embedded industries, consumers will likely only experience one firsthand when it's integrated into an Android handset. Since Android 4.0, Google has supported three ISAs: x86, ARM, and MIPS. Several devices have shipped running MIPS processors, most notably the low-cost Novo 7 tablet. MIPS devices will continue to be low cost alternative devices for now, but low cost devices have the largest volume. The volume should eventually help MIPS push app developers to address their #1 problem: compatibility.

Android applications are either written in Java, then compiled on the device to the specific required ISA before running (a processes called JIT compilation), or written in the Android Native Development Kit (NDK) to target a specific ISA. Apps written in Java can therefore run on any ISA that Android itself supports, including MIPS. Apps written with the NDK (many of which exist, especially games) cannot run on anything but the specific ISA they were written for. The Android NDK does allows packaging multiple ISA specific binaries into a single app, but with the vast majority of Android devices using ARM processors and therefore the ARM ISA, a multiple NDK Android app is simply uncommon.

What does this mean for an end user? There are many Android apps that simply won’t run if you have a MIPS processor in your device. Intel has the same NDK compatibility problem, but with their considerably larger engineering resources, Intel implemented a layer that translates ARM ISA applications to the Intel x86 ISA (albeit at a performance penalty). Until MIPS implements the same or ships enough volume to convince Android app developers to put in some extra work, a MIPS Android device will unfortunately be a second class experience.

Despite some existing Android app compatibility woes, the MIPS I6400 CPU contains some interesting technology designed to address many more markets than handsets. In fact, Android usage of MIPS processors is really a minor part of the MIPS business. A few slides from the MIPS announcement indicate just how many other markets they are targeting.

Introduction The MIPS I6400 CPU
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  • Exophase - Wednesday, September 3, 2014 - link

    Hi Alex, could you clarify what you mean by this comment? Superscalar and in-order are completely orthogonal properties, and I would expect that it always behaves like an in-order design regardless of SMT. Do you mean that in SMT mode it can only dispatch one instruction per cycle from the same thread? If that's the case, surely this is something that can be dynamically configured based on active thread count and not a fixed property of the processor? Reply
  • MartinT - Thursday, September 4, 2014 - link

    I guess it is true strictly speaking that because of the two execution queues, it's limited to either super-scalar (single-threaded) or (scalar) multi-threaded operation at any one instant.

    I agree that it should read 'scalar' rather than 'in-order'.
    Reply
  • mthrondson - Sunday, September 7, 2014 - link

    To clarify - the I6400 can run superscalar on a single thread, or issue from two threads simultaneously. And it can switch which thread(s) it is working from on a per cycle basis. Reply
  • Guspaz - Tuesday, September 2, 2014 - link

    They taught us MIPS32 assembly in school. My impression was that it was enormously simpler to write by hand than x86 assembly, much less of a headache to work with. Of course, assembly is almost entirely irrelevant these days. Reply
  • patrickjchase - Tuesday, September 2, 2014 - link

    The main reason everybody learns MIPS (a.k.a. "DLX") in school is because the dominant architecture text was co-written by MIPS' inventor. Reply
  • Guspaz - Tuesday, September 2, 2014 - link

    That's entirely possible. To be honest, I don't remember which textbook we used for our processor architecture course. But it was a breath of fresh air compared to x86 or even SIC. Having all the registers be general-purpose and letting you specify which register to put results into in the instruction was much easier to work with when writing assembly by hand on paper than x86, where every register seemed to be special-purpose, with different instructions putting results in different abstractly named registers. Reply
  • Exophase - Wednesday, September 3, 2014 - link

    I've written x86 and MIPS assembly in real world applications, and personally I find both to be pretty annoying. When writing MIPS assembly, the poor addressing modes, delay slots, and range of immediates make it more cumbersome than x86. When writing x86 assembly, the lack of registers and three-address operands make it more cumbersome than MIPS. I haven't written much in x86-64, which I suspect is less annoying. Reply
  • dwforbes - Tuesday, September 2, 2014 - link

    It's worth noting that for Android developers using the NDK, coding for MIPS, ARM64, or x86-64, is in the vast majority of cases nothing more than a compiler flag. There is seldom extra work necessary unless you've specifically used inline assembly. Reply
  • Samastrike - Tuesday, September 2, 2014 - link

    I couldn't help noticing that the android logo used in the slide on the second page is holding a lollipop. Is this some confirmation of the official name when android L releases? Reply
  • Stephen Barrett - Tuesday, September 2, 2014 - link

    I had the same thought. Wondered if someone would notice that. I'll let everyone conjecture on that topic :) Reply

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