Marvell Announces 112G SerDes, Built on TSMC 5nmby Dr. Ian Cutress on November 17, 2020 8:45 AM EST
So far we have three products in the market built on TSMC’s N5 process: the Huawei Kirin 9000 5G SoC, found in the Mate 40 Pro, the Apple A14 SoC, found in the iPhone 12 family, and the Apple M1 SoC, which is in the new MBA/MBP and Mac Mini. We can now add another to that list, but it’s not a standard SoC: here we have IP for a SerDes connection, now validated and ready for licensing in TSMC N5. Today Marvell is announcing its DSP-based 112G SerDes solution for licensing.
Modern chip-to-chip networking infrastructure relies on high speed SerDes connections to enable a variety of different protocols at a range of speeds, typically in Ethernet, fiber optics, storage, and connectivity fabrics. Current high-speed connections rely on 56G connections, and so moving up to 112G enables double the speed. Several companies have 112G IP available, however Marvell is the first to enable it in 5nm, ensure it is hardware validated, and offer it for licensing.
These sorts of connections have a number of measurements to compare them to other 112G solutions: the goal is to not only meet the standard, but offer a solution that uses less power, but also a lower potential error rate, especially for high-speed high-reliability infrastructure applications. Marvell is claiming that its new solution enables a significant power reduction in energy per bit transferred – up to 25% compared to equivalent TSMC 7nm offerings, along with tight power/thermal constraints and a >40dB insertion loss.
We typically expect data to travel down a connection like this as a series of ones and zeros, i.e. a 1-bit operation which can be a 0 or a 1, known as NRZ (non-return to zero) - however Marvell’s solution enables 2-bit operation, such as a 00, 01, 10, or 11, known as PAM4 (Pulse Amplitude Modulation). This enables double the bandwidth, but does require some extra circuitry. PAM4 has been enabled at lower SerDes speeds and at 112G before, but not for TSMC N5. As we move to even faster speeds, PAM4 will become a necessity to enable them. Regular readers may identify that NVIDIA’s RTX 3090 uses PAM4 signaling (on N7) to enable over 1000 GB/s of bandwidth with Micron’s GDDR6X – it can also be run in NRZ mode for lower power if needed.
Marvell says it is already engaged with its custom ASIC customers across multiple markets with the 112G implementation. Alongside the new 112G SerDes, the company says it is set to enable a complete suite of PHYs, switches, DPUs, custom processors, controllers, and accelerators built on 5nm, and that this initial offering is but the first step.
- ‘Better Yield on 5nm than 7nm’: TSMC Update on Defect Rates for N5
- TSMC Boosts CapEx by $1 Billion, Expects N5 Node to Be Major Success
- Apple Announces The Apple Silicon M1: Ditching x86 - What to Expect, Based on A14
- Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020
- Huawei Announces Mate 40 Series: Powered by 15.3bn Transistors 5nm Kirin 9000
- Intel Launches Stratix 10 TX: Leveraging EMIB with 58G Transceivers
- Intel’s New 224G PAM4 Transceivers
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DigitalFreak - Tuesday, November 17, 2020 - linkIs SerDes anything like HerpDerp?
Holliday75 - Tuesday, November 17, 2020 - linkA quick google search comes up empty.
AdrianBc - Tuesday, November 17, 2020 - linkSerDes is modern lingo for a device that converts between serial (i.e. on a single wire) and parallel (i.e. on multiple wires) data transmission.
Every complex digital device, e.g. a CPU or a GPU, contains many SerDes, which convert between the internal parallel data transmission and the external serial data transmission, which is usually done on standardized serial interfaces, e.g. Ethernet, PCI Express, SATA, USB and others.
chrysrobyn - Wednesday, November 18, 2020 - linkSerDes = Serializer / Deserializer. It's a thing used to take a wide data bus and shove it into a serial link, and then expand it out again on the other side.
Think about DDR or PCIE needing to take all their data an protocol stuff into a funnel just before it leaves the chip and goes out to the board, and then how it needs to expand out again when it gets to its destination.
Mr Perfect - Tuesday, November 17, 2020 - link"Regular readers may identify that NVIDIA’s RTX 3090 uses PAM4 signaling (on N7) to enable over 1000 GB/s of bandwidth with Micron’s GDDR6X"
No, sorry. I haven't read the 30 series Deep Dive yet. :P
Ryan is still doing one, right?
Mr Perfect - Tuesday, November 17, 2020 - linkOkay, I see PAM4 was discussed in the 30 series announcement briefing. Serves me right for being snarky.
PeachNCream - Tuesday, November 17, 2020 - linkIt doesn't make it any less funny, though it would be nice to see AT covering more high end components AND more low end/budget computers as well.
kmob - Tuesday, November 17, 2020 - linkI noticed from that article that Nvidia is using PAM4 signaling at only 50Gb / second though - so less than half of this Marvell announcement. While they both use PAM4 signaling, this is significantly faster for each link, and in N5.
azfacea - Tuesday, November 17, 2020 - linkthe age of terabit Ethernet is here. meanwhile some1 at intel is strategizing "next Gen" motherboards w/ exciting gigabit ports and moar ME backdoors
ksec - Wednesday, November 18, 2020 - linkI know this is great for 400G Ethernet, but why do we not have 5nm SerDes for 10GBse-T Ethernet to try and bring down power consumption per port? Are the 10G Ethernet market that small the is not worth the investment?